A central processing unit (CPU) is the part of a computer that interprets and carries out instructions contained in software, which can have various functions such as controlling hardware, performing computations, and communication with other software. The timing execution of instructions may vary, depending on a number of various conditions (e.g., status register contents, the value of a bit, the size of the following instructions, accessed peripherals, etc.).
Variations in timing execution can be a serious problem when the timing must be constant or predictable. For example, during software communication routines, a co-processor must be synchronized with the CPU. Timing variations can also cause problems such as the leakage of sensitive information, etc.
Generally, known solutions are unreliable and time consuming to implement. For example, software routines are developed and manually balanced in Assembly Language to ensure that all possible paths execute in an equal number of clock cycles. This is an error prone and time-consuming process that also induces high maintenance costs and risks.
Accordingly, what is needed is an improved method and system for controlling timing in a CPU. The present invention addresses such a need.